1. Field of the Invention
The present invention relates to a receiving apparatus, a receiving method, and a program and, more particularly, to a receiving apparatus, a receiving method, and a program that are configured to correctly detect the capture of a receive signal.
2. Description of the Related Art
Receiving apparatuses configured to receive digital broadcast and so on must execute, in receiving broadcast waves and digitally demodulating receive signals thereof, timing correction and phase noise correction on the receive signals, for example. Generally, these correction processing operations are seamlessly executed by a correction circuit that is configured to execute automatic control based on control engineering.
For example, FIG. 1 shows a block diagram illustrating a related-art correction circuit.
As shown in FIG. 1, a correction circuit 11 is made up of a correction block 12, an error detector 13, a loop filter 14, an NCO (Numerically Controlled Oscillator) 15, thereby forming a feedback loop.
The correction block 12 is supplied with a receive signal received at a receiving circuit having an antenna, not shown. The correction block 12 executes correction processing for removing an error (a frequency error or a phase error) of the receive signal on the basis of an error correction signal supplied from the NCO 15. Next, the correction block 12 supplied the corrected receive signal to the error detector 13 and, at the same time, outputs the corrected receive signal to a signal processing circuit 21 of a subsequent stage, such as a demodulating circuit or a decoding circuit, for example.
The error detector 13 detects an error of the corrected receive signal supplied from the correction block 12 and supplies the detected error to the loop filter 14. The loop filter 14 filters the error signal supplied from the error detector 13 for smoothing and supplies the smoothed signal to the NCO 15. In accordance with the error signal supplied from the loop filter 14, the NCO 15 controls the oscillation frequency of the error correction signal to be supplied to the correction block 12, generating an error correction signal having an oscillation frequency in accordance with the error.
Then, when the receive signal is corrected in the correction block 12 on the basis of the error correction signal supplied from the NCO 15, the error of the receive signal to be outputted from the correction block 12 is reduced. When the reduced error falls within a predetermined error range, the correction of the receive signal is completed. Namely, the receive signal is captured.
As described above, when a receive signal is captured, the correction circuit 11 goes from the initial capture processing for capturing a receive signal to the synchronization hold processing for holding the synchronization of the captured receive signal. At the same time, in the receiving apparatus, a lock signal indicative that the receive signal has been captured in the correction circuit 11 is supplied to the signal processing circuit 21 of the subsequent stage.
The receiving apparatus shown in FIG. 2 has a lock detector 22 configured to output a lock signal.
In FIG. 2, the lock detector 22 is supplied with an error signal outputted from the error detector 13. The lock detector 22 monitors this error signal and, when the error of the receive signal falls within a predetermined error range, supplies a lock signal indicative of that the receive signal has been captured to the signal processing circuit 21.
For example, timing recovery (or timing correction) is executed by use of an interpolation filter as the correction block 12 and a timing phase error detector as the error detector 13.
FIG. 3 shows a block diagram illustrating an exemplary configuration of a correction circuit 11′ configured to execute timing recovery.
In the correction circuit 11′, a timing phase error detector 17 detects a timing phase error of a receive signal outputted from an interpolation filter 18 and an error correction signal based on this timing phase error is supplied from an NCO 15 to the interpolation filter 18. Next, in accordance with the error correction signal supplied from the NCO 15, the interpolation filter 18 adjusts the timing of the frequency for sampling the receive signal, thereby correcting the timing deviation of the receive signal. Next, the lock detector 22 monitors the timing phase error outputted from the timing phase error detector 17 and, when the receive signal is captured, supplies the lock signal to the signal processing circuit 21.
Also, Japanese Patent Laid-open No. 2002-94585 discloses a receiving apparatus configured to adjust the gain of a loop filter on the basis of an error detection result of a receive signal, for example.